The present invention relates to integrated circuits, systems and fabrication processes and more particularly to a method and system for modeling uncertainties in integrated circuits, systems, fabrication processes or the like.
Manufacturing process variations are random and the true causes may be complicated. In general, the variations may be classified into two categories: global variations and local variations. Global variations, such as critical-dimension variations, are inter-die and can be assumed to affect all the devices and interconnections in a similar way across several different semiconductor chips or wafers. Local variations, such as metal width and thickness variations, are intra-die and often exhibit spatial correlations. For example, the device and interconnect parameters may be affected similarly by a common source of variation when these physical elements are close enough to each other. In the past, global variations dominated local variations but as semiconductor technology scales and die sizes grow, local variations are becoming as important as global variations. At 90 nanometers (nm) and below, device and interconnect parameters can no longer be regarded as being deterministic. The increasing atomic scale of manufacturing causes design parameters to be statistically distributed with complex correlations. The challenge is how to efficiently analyze critical devices, interconnects and circuit layouts under these circumstances.